I think the main decider here could be financial.

If backside power requires say 10 more imaging steps, then for a given number of imaging machines you can produce fewer wafers per month.

If there is strong demand for the new process (which, since it'll be industry leading I'm sure there will be), you make more money if you can produce more wafers per month but missing a feature.

As demand reduces and more imaging machines get delivered, then it makes sense to add in backside power again.

Is my memory mistaken but I thought that originally the N2 was suppose to be released this year. And because it wasn't, and instead pushed to next year, it disrupted Apples plans with the M2.

But looking at timeline, it says N2 isn't available now until 2025.

Is my memory wrong that N2 was suppose to be 2022, then pushed to 2023?

I hope Intel get their act together and start manufacturing ARM chips designed by Apple for Apple. Competition will push TSMC even harder to innovative faster to stay ahead.
Power is an interesting part of the trend for TSMC -- 4 generations of 30% power reduction -- so that should result in a 75% reduction in power -- so where you burned 10W before, you now burn only 2.5W -- but does that mean you get the lower power and the better perf as well? I would assume its 75% power reduction for the performance of 7nm node -- not positive though..
Maybe Intel is correct in trying to do this in one go. Maybe TSMC knows something about EUVL that Intel doesn't.
Why is a month and a half old article trending on HN?